1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which includes a trench capacitor.
2. Description of the Related Art
In the semiconductor memory device, a gate electrode and an active area of an array transistor of a memory cell, e.g., a source, a drain, and a channel region, are formed to be planar in a surface of a semiconductor substrate. In a dynamic random memory (DRAM), for example, a size of one memory cell is 8F2 or 6F2 in most cases. Where, F denotes a critical dimension of a lithography technology used. Thus, in the semiconductor memory device, progress has been made in reductions of a cell size and a chip size by shrinking critical dimensions.
However, as shrinking the critical dimensions, a gate length of the transistor also decreases, therefore deterioration occurs in cut-off characteristics of the array transistor.
To achieve a high density semiconductor memory device, a memory cell structure that uses a vertical transistor is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-2614. According to this structure, a storage capacitor having an n-type polysilicon is formed in a bottom of a deep trench formed in a semiconductor substrate, and a gate electrode of the vertical transistor is disposed in its upper trench. A source, a channel region, and a drain of the vertical transistor are vertically disposed side by side in the semiconductor substrate of one side face of the trench facing the gate electrode. Hence, a size of the memory cell is reduced to 6F2. However, such a memory cell has a process problem that a deep trench must be formed. Additionally, further progress in miniaturization causes a problem that holes are accumulated in the channel region to destabilize the vertical transistor operation.
A memory cell of another structure that actively uses holes accumulated in a channel region is a floating body cell (referred as FBC, herein after) (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-335031). The FBC memory is a memory cell which does not use a capacitor but utilizes a characteristic in which a threshold voltage of n channel transistor lowers when holes are accumulated in the channel region. The memory cell is mainly used in a semiconductor memory device using a silicon-on-insulator (SOI) substrate. In an SOI semiconductor memory device, as the channel region (body) is formed on an insulator, the channel region is inevitably set in a floating state. In the case of the FBC, it can hardly increase a storage capacity because of a limitation of an area of the channel region to store the holes.